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general description the max5723/max5724/max5725 8-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (dacs) include output buffers and an internal 3ppm/c reference that is selectable to be 2.048v, 2.500v, or 4.096v. the max5723/max5724/max5725 accept a wide supply voltage range of 2.7v to 5.5v with extremely low power (6mw) consumption to accommodate most low-voltage applications. a precision external reference input allows rail-to-rail operation and presents a 100k i (typ) load to an external reference. the max5723/max5724/max5725 have a fast 50mhz, 4-wire spi/qspi?/microwire ? /dsp-compatible serial interface that operates at clock rates up to 50mhz. the dac output is buffered and has a low supply current of less than 250 f a per channel and a low offset error of q 0.5mv (typ). on power-up, the max5723/max5724/ max5725 reset the dac outputs to zero or midscale based on the status of m/ z logic input, providing flex - ibility for a variety of control applications. the internal reference is initially powered down to allow use of an external reference. the max5723/max5724/max5725 allow simultaneous output updates using software load commands or the hardware load dac logic input ( ldac ). the max5723/max5724/max5725 feature a program - mable watchdog function which can be enabled to moni - tor the i/o interface for activity and integrity. a clear logic input ( clr ) allows the contents of the code and the dac registers to be cleared asynchronously and simultaneously sets the dac outputs to the program - mable default value. the max5723/max5724/max5725 are available in a 20-pin tssop and an ultra-small, 20-bump wlp package and are specified over the -40 n c to +125 n c temperature range. applications programmable voltage and current sources gain and offset adjustment automatic tuning and optical control power amplifier control and biasing process control and servo loops portable instrumentation benefits and features s eight high-accuracy dac channels ? 12-bit accuracy without adjustment ? 1 lsb inl buffered voltage output ? guaranteed monotonic over all operating conditions ? independent mode settings for each dac s three precision selectable internal references ? 2.048v, 2.500v, or 4.096v s internal output buffer ? rail-to-rail operation with external reference ? 4.5s settling time ? outputs directly drive 2k i loads s small 6.5mm x 4.4mm 20-pin tssop or ultra- small 2.5mm x 2.3mm 20-bump wlp package s wide 2.7v to 5.5v supply range s separate 1.8v to 5.5v v ddio power-supply input s fast 50mhz 4-wire spi/qspi/microwire/dsp- compatible serial interface s programmable interface watchdog timer s pin-selectable power-on-reset to zero-scale or midscale dac output s ldac and clr for asynchronous dac control s three selectable power-down output impedances ? 1k i , 100k i , or high impedance 19-6243; rev 2; 2/13 ordering information appears at end of data sheet . functional diagram qspi is a trademark of motorola, inc. microwire is a registered trademark of national semiconductor c orporation. max is a registered trademark of maxim integrated products, inc. din sclk csb out0 buffer por watchdog timer v dd gnd dac control logic power-down ref out1 out2 out3 out4 out5 out6 out7 v ddio dout clr ldac irq m/z spi serial interface 1ki 100ki code load clear/ reset (gate/ clear / reset) code register dac latch 8- /1 0- / 12-bit dac 1 of 8 dac channels internal reference/ external buffer max5723 max5724 max5725 for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max5723.related max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 v dd , v ddio to gnd ................................................ -0.3v to +6v out_, ref to gnd ....0.3v to the lower of (v dd + 0.3v) and +6v sclk, csb, irq, m /z, ldac, clr to gnd ........... -0.3v to +6v din, dout to gnd ..................................... -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70 n c) tssop (derate at 13.6mw/ n c above 70 n c) .............. 1084mw wlp (derate at 21.3mw/ n c above 70 n c) .................. 1700mw maximum continuous current into any pin .................... q 50ma operating temperature .................................... -40 n c to +125 n c storage temperature ....................................... -65 n c to +150 n c lead temperature (tssop only)(soldering, 10s) ........... +300 n c soldering temperature (reflow) .................................... +260 n c tssop junction-to-ambient thermal resistance ( ja ) ...... 73.8 n c/w junction-to-case thermal resistance ( jc ) .............. 20 n c/w wlp junction-to-ambient thermal resistance ( ja ) (note 2) ................................................................... 47 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . note 2: visit www.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of wlp packaging. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units dc performance (note 4) resolution and monotonicity n max5723 8 bits max5724 10 max5725 12 integral nonlinearity (note 5) inl max5723 -0.25 q 0.05 +0.25 lsb max5724 -0.5 q 0.2 +0.5 max5725 -1 q 0.5 +1 differential nonlinearity (note 5) dnl max5723 -0.25 q 0.05 +0.25 lsb max5724 -0.5 q 0.1 +0.5 max5725 -1 q 0.2 +1 offset error (note 6) oe -5 q 0.5 +5 mv offset error drift q 10 f v/ n c gain error (note 6) ge -1.0 q 0.1 +1.0 %fs gain temperature coefficient with respect to v ref q 3.0 ppm of fs/ n c max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
3 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units zero-scale error 0 +10 mv full-scale error with respect to v ref -0.5 +0.5 %fs dac output characteristics output voltage range (note 7) no load 0 v dd v 2k i load to gnd 0 v dd - 0.2 2k i load to v dd 0.2 v dd load regulation v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 300 f v/ma v dd = 5v q 10%, |i out | p 10ma 300 dc output impedance v out = v fs /2 v dd = 3v q 10%, |i out | p 5ma 0.3 i v dd = 5v q 10%, |i out | p 10ma 0.3 maximum capacitive load handling c l 500 pf resistive load handling r l 2 k i short-circuit output current v dd = 5.5v sourcing (output shorted to gnd) 30 ma sinking (output shorted to v dd ) 50 dc power-supply rejection v dd = 3v q 10% or 5v q 10% 100 f v/v dynamic performance voltage-output slew rate sr positive and negative 1.0 v/ f s voltage-output settling time ? scale to ? scale, to p 1 lsb, max5723 2.2 f s ? scale to ? scale, to p 1 lsb, max5724 2.6 ? scale to ? scale, to p 1 lsb, max5725 4.5 dac glitch impulse major code transition (code x7ff to x800) 7 nv*s channel-to-channel feedthrough (note 8) internal reference 3.3 nv*s external reference 4.07 digital feedthrough midscale code, all digital inputs from 0v to v ddio 0.2 nv*s power-up time startup calibration time (note 9) 200 f s from power-down 50 f s max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
4 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units output voltage-noise density (dac output at midscale) external reference f = 1khz 90 nv/ hz f = 10khz 82 2.048v internal reference f = 1khz 112 f = 10khz 102 2.5v internal reference f = 1khz 125 f = 10khz 110 4.096v internal reference f = 1khz 160 f = 10khz 145 integrated output noise (dac output at midscale) external reference f = 0.1hz to 10hz 12 f v p-p f = 0.1hz to 10khz 76 f = 0.1hz to 300khz 385 2.048v internal reference f = 0.1hz to 10hz 14 f = 0.1hz to 10khz 91 f = 0.1hz to 300khz 450 2.5v internal reference f = 0.1hz to 10hz 15 f = 0.1hz to 10khz 99 f = 0.1hz to 300khz 470 4.096v internal reference f = 0.1hz to 10hz 16 f = 0.1hz to 10khz 124 f = 0.1hz to 300khz 490 output voltage-noise density (dac output at full scale) external reference f = 1khz 114 nv/ hz f = 10khz 99 2.048v internal reference f = 1khz 175 f = 10khz 153 2.5v internal reference f = 1khz 200 f = 10khz 174 4.096v internal reference f = 1khz 295 f = 10khz 255 integrated output noise (dac output at full scale) external reference f = 0.1hz to 10hz 13 f v p-p f = 0.1hz to 10khz 94 f = 0.1hz to 300khz 540 2.048v internal reference f = 0.1hz to 10hz 19 f = 0.1hz to 10khz 143 f = 0.1hz to 300khz 685 2.5v internal reference f = 0.1hz to 10hz 21 f = 0.1hz to 10khz 159 f = 0.1hz to 300khz 705 4.096v internal reference f = 0.1hz to 10hz 26 f = 0.1hz to 10khz 213 f = 0.1hz to 300khz 750 max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
5 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units reference input reference input range v ref 1.24 v dd v reference input current i ref v ref = v dd = 5.5v 55 74 f a reference input impedance r ref 75 100 k i reference output reference output voltage v ref v ref = 2.048v, t a = +25 n c 2.043 2.048 2.053 v v ref = 2.5v, t a = +25 n c 2.494 2.500 2.506 v ref = 4.096v, t a = +25 n c 4.086 4.096 4.106 reference temperature coefficient (note 10) max5725a q 3 q 10 ppm/ n c max5723/max5724/max5725b q 10 q 25 reference drive capacity external load 25 k i reference capacitive load handling 200 pf reference load regulation i source = 0 to 500 f a 2 mv/ma reference line regulation 0.05 mv/v power requirements supply voltage v dd v ref = 4.096v 4.5 5.5 v all other options 2.7 5.5 i/o supply voltage v ddio 1.8 5.5 v supply current (note 11) i dd internal reference v ref = 2.048v 1.6 2 ma v ref = 2.5v 1.7 2.1 v ref = 4.096v 2.0 2.5 external reference v ref = 3v 1.6 2.0 v ref = 5v 1.9 2.5 power-down mode supply current i pd all dacs off, internal reference on 140 f a all dacs off, internal reference off, t a = -40 n c to +85 n c 0.7 2 all dacs off, internal reference off, t a = +125 n c 2 4 digital supply current i ddio static logic inputs, all outputs unloaded 1 f a digital input characteristics (sclk, din, csb, ldac , clr, m /z ) input leakage current i in v in = 0v or v ddio , all inputs except m/ z (note 11) q 0.1 q 1 f a v in = 0v or v dd , for m/ z (note 11) max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
6 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units input high voltage v ih (all inputs except m/ z ) 2.2v < v ddio < 5.5v 0.7 x v ddio v 1.8v < v ddio < 2.2v 0.8 x v ddio v 2.7v < v dd < 5.5v (for m/ z ) 0.7 x v dd input low voltage v il (all inputs except m/ z ) 2.2v < v ddio < 5.5v 0.3 x v ddio v 1.8v < v ddio < 2.2v 0.2 x v ddio v 2.7v < v dd < 5.5v (for m/ z ) 0.3 x v dd input capacitance (note 10) c in 10 pf hysteresis voltage v h 0.15 v digital output ( irq ) output low voltage v ol i sink = 3ma 0.2 v output inactive leakage i off q 0.1 q 1 f a output inactive capacitance (note 10) c off 10 pf digital output (dout) output high voltage v oh v ddio > 2.5v, i source = 3ma v ddio - 0.2 v v ddio > 1.8v, i source = 2ma v ddio - 0.2 output low voltage v ol v ddio > 2.5v, i sink = 3ma 0.2 v v ddio > 1.8v, i sink = 2ma 0.2 output short-circuit current i oss i sink , i source 100 ma output three-state leakage i oz 0.1 1 a output three-state capacitance c oz 10 pf watchdog timer characteristics watchdog timer period t wdosc v dd = 3v, t a = +25c 0.95 1 1.05 ms watchdog timer period supply drift v dd = 2.7v to 5.5v, t a = +25c 0.6 %/v watchdog timer period temperature drift v dd = 3v 0.0375 %/c max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
7 electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units spi timing characteristics sclk frequency f sclk 2.7v < v ddio < 5.5v write mode 0 50 mhz read mode, strobing on 1 sclk 0 25 read mode, strobing on ? sclk 0 12.5 1.8v < v ddio < 2.7v write mode 0 33 read mode, strobing on 1 sclk 0 20 read mode, strobing on ? sclk 0 10 sclk period t sclk 2.7v < v ddio < 5.5v, write mode 20 ns 1.8v < v ddio < 2.7v, write mode 30 sclk pulse width high t ch 8 ns sclk pulse width low t cl 8 ns csb fall to sclk fall setup time t css0 to first sclk falling edge 2 .7v < v ddio < 5.5v 8 ns 1.8v < v ddio < 2.7v 12 csb fall to sclk fall hold time t csh0 applies to inactive sclk falling edge preceding the first sclk falling edge 0 ns csb rise to sclk fall hold time t csh1 applies to the 24 th sclk falling edge 0 ns csb rise to sclk fall t csa applies to the 24 th sclk falling edge , aborted sequence 12 ns sclk fall to csb fall t csf a pplies to 24th sclk falling edge 100 ns csb pulse width high t cspw 20 ns din to sclk fall setup time t ds 5 ns din to sclk fall hold time t dh 4.5 ns clr pulse width low t clpw 20 ns clr rise to csb fall t csc required for command to be executed 20 ns ldac pulse width low t ldpw 20 ns ldac fall to sclk fall hold t ldh a pplies to 24th sclk falling edge 20 ns sclk fall to dout transition t dot dpha = 0, c load = 20pf 2 .7v < v ddio < 5.5v 35 ns 1.8v < v ddio < 2.7v 40 sclk rise to dout transition t dot dpha = 1, c load = 20pf 2 .7v < v ddio < 5.5v 35 ns 1.8v < v ddio < 2.7v 40 max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
8 note 3: electrical specifications are production tested at t a = +25c. specifications over the entire operating temperature range are guaranteed by design and characterization. typical specifications are at t a = +25c. note 4: dc performance is tested without load, v ref = v dd . note 5: linearity is tested with unloaded outputs to within 20mv of gnd and v dd . note 6: gain and offset calculated from measurements made with v ref = v dd at codes 30 and 4065 for max5725, codes 8 and 1016 for max5724, and codes 2 and 254 for max5723. note 7: subject to zero- and full-scale error limits and v ref settings. note 8: measured with all other dac outputs at midscale with one channel transitioning 0 to full scale. note 9: on power-up, the device initiates an internal 200s (typ) calibration sequence. all commands issued during this time will be ignored. note 10: guaranteed by design. note 11: all channels active at v fs , unloaded. static logic inputs with v il = v gnd and v ih = v ddio for all inputs. electrical characteristics (continued) (v dd = 2.7v to 5.5v, v ddio = 1.8v to 5.5v, v gnd = 0v, c l = 200pf, r l = 2k i , t a = -40 n c to +125 n c, unless otherwise noted.) (note 3) figure 1. spi serial interface timing diagram parameter symbol conditions min typ max units sclk fall to dout hold t doh dpha = 0, c load = 0pf 2 ns sclk rise to dout hold t doh dpha = 1, c load = 0pf 2 ns csb fall to dout fall t doe enable time, c load = 20pf 20 ns csb rise to dout hi-z t doz disable time 2 .7v < v ddio < 5.5v 20 ns 1.8v < v ddio < 2.7v 40 d in 23 12 din sclk csb dout (dpha = 1) dout (dpha = 0) t ds t dh t cl t csa t csh1 t doz t doh t csf z z t ch t csh0 z z t cspw t doe t clpw t csc t css0 t sclk 34 56 78 91 02 32 41 d in 22 d in 21 d in 20 d in 19 d in 18 d in 17 d in 16 d in 15 d in 14 d o 15 d o 1 d o 0 d in 1 d in 0 d in 23? d o 15 d o 14 d o 1 d o 0 t ldh t ldpw t dot t dot t doh clr ldac max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
9 typical operating characteristics (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) inl vs. code max5723 toc01 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load inl vs. code max5723 toc02 code (lsb) inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load dnl vs. code max5723 toc03 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 3v no load offset and zero-scale error vs. supply voltage max5723 toc07 supply voltage (v) error (mv) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.7 5.5 zero-scale error offset error v ref = 2.5v (external) no load dnl vs. code max5723 toc04 code (lsb) dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 v dd = v ref = 5v no load inl and dnl vs. supply voltage max5723 toc05 supply voltage (v) error (lsb) 5.1 4.7 3.9 4.3 3.5 3.1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 max inl v dd = v ref 1.0 -1.0 2.7 5.5 max dnl min dnl min inl inl and dnl vs. temperature max5723 toc06 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (lsb) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 max inl v dd = v ref = 3v max dnl min dnl min inl max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
10 typical operating characteristics (continued) (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) full-scale error and gain error vs. temperature max5723 toc10 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (%fsr) -0.05 0 0.05 0.10 -0.10 v ref = 2.5v (external) no load gain error (v dd = 3v) gain error (v dd = 5v) full-scale error supply current vs. temperature max5723 toc11 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 supply current (ma) 1.2 1.4 1.6 2.0 1.8 1.0 v ref (external) = v dd = 5v v dd = v ddio v out_ = full scale all dacs enabled no load v ref (internal) = 4.096v, v dd = 5v v ref (internal) = 2.5v, v dd = 5v v ref (internal) = 2.048v, v dd = 5v v ref (external) = v dd = 3v supply current vs. supply voltage max5723 toc12 supply voltage (v) supply current (ma) 5.1 4.7 3.9 4.3 3.5 3.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 2.7 5.5 v dd = v ddio v out_ = full scale all dacs enabled no load v ref (internal) = 4.096v v ref (internal) = 2.5v v ref (internal) = 2.048v v ref = 2.5v (external) power-down mode supply current vs. supply voltage max5723 toc13 supply voltage (v) power-down supply current (a) 5.1 4.7 4.3 3.9 3.5 3.1 0.4 0.8 1.2 1.6 2.0 0 2.7 5.5 t a = -40c t a = +25c t a = +85c t a = +125c v dd = v ddio v ref = 2.5v (external) power-down mode with hi-z no load offset and zero-scale error vs. temperature max5723 toc08 temperature (c) 110 95 65 80 -10 5 20 35 50 -25 -40 125 error (mv) -0.8 -0.6 -0.4 -0.2 0.2 0 0.4 0.6 0.8 1.0 -1.0 v ref = 2.5v (external) no load offset error (v dd = 5v) offset error (v dd = 3v) zero-scale error full-scale error and gain error vs. supply voltage max5723 toc09 supply voltage (v) error (%fs) 5.1 4.7 3.9 4.3 3.5 3.1 -0.016 -0.012 -0.008 -0.004 0 0.004 0.008 0.012 0.016 v ref = 2.5v (external) no load 0.020 -0.020 2.7 5.5 full-scale error gain error max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
11 typical operating characteristics (continued) (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) i vdd vs. code max5723 toc14 code (lsb) supply current (ma) 3584 3072 2560 2048 1536 1024 0.4 0.8 1.2 1.6 2.0 0 512 0 4096 v dd = 5v, v ref = 4.096v v dd = v ref = 3v v dd = 5v, v ref = 2.048v v dd = 5v, v ref = 2.5v v dd = v ref = 5v no load i ref (external) vs. code max5723 toc15 code (lsb) reference current ( a) 3584 3072 2560 2048 1536 1024 10 20 30 40 50 60 0 512 0 4096 v dd = v ref no load v ref = 5v v ref = 3v max5723 toc16 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3.75s 1/4 scale to 3/4 scal e max5723 toc17 trigger pulse 5v/div v out 0.5v/div zoomed v out 1 lsb/div 4s/div settling to 1 lsb (v dd = v ref = 5v, r l = 2ki , c l = 200pf) 3/4 scale to 1/4 scal e 4.3s major code transition glitch energy (v dd = v ref = 5v, r l = 2ki , c l = 200pf) max5723 toc18 v out 3.3mv/div trigger pulse 5v/div 1 lsb change (midcode transition from 0x7ff to 0x800) glitch energy = 6.7nv*s major code transition glitch energy (v dd = v ref = 5v, r l = 2ki, c l = 200pf) max5723 toc19 v out 3.3mv/div trigger pulse 5v/div 1 lsb change (midcode transition from 0x800 to 0x7ff) glitch energy = 6nv*s 2s/div max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
12 typical operating characteristics (continued) (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) v out vs. time transient exiting power-down max5723 toc20 dac output 500mv/div 10s / div v sclk 5v/div 0v 24th edge 0v v dd = 5v, v ref = 2.5v external power-on reset to 0v max5723 toc21 v out 2v/div 20s / div v dd 2v/div 0v 0v v dd = v ref = 5v 10ki load to v dd channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, r l = 2ki , c l = 200pf) max5723 toc24 4s / div v out0 5v/div loaded v out4 0.585 lsb/div no load transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 4.07nv*s max5723 toc25 v out0 5v/div loaded v out4 0.585 lsb/div no load 4s/div channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v (internal), t a = +25n c, r l = 2ki , c l = 200pf) transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s channel-to-channel feedthrough (v dd = v ref = 5v, t a = +25n c, no load) max5723 toc22 4s / div v out0 5v/div no load v out4 0.585 lsb/div no load transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 3.3nv*s channel-to-channel feedthrough (v dd = 5v, v ref = 4.096v, t a = +25n c, no load) max5723 toc23 4s / div v out0 5v/div no load v out4 0.585 lsb/div no load transitioning dac: 0 to full scale static dac: midscale analog crosstalk = 2.6nv*s max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
13 typical operating characteristics (continued) (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) digital feedthrough (v dd = v ref = 5v, r l = 10ki) max5723 toc26 2.5mv/div 20ns/div v ref = 4.096v (internal) digital crosstalk = 0.2nv*s output load regulation max5723 toc27 i o ut (ma) d v out (mv) 50 40 20 30 -10 0 10 -20 -8 -6 -4 -2 0 2 4 6 8 10 -10 -30 60 v dd = v ref v dd = 5v v dd = 3v output current limiting max5723 toc28 i out (ma) d v out (mv) 60 50 30 40 -10 0 10 20 -20 -400 -300 -200 -100 0 100 200 300 400 500 -500 -30 70 v dd = v ref v dd = 5v v dd = 3v headroom at rails vs. output current (v dd = v ref ) max5723 toc29 i out (ma) v out (v) 9 8 6 7 2 3 4 5 1 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 0 01 0 v dd = 5v, sourcing v dd = 3v, sourcing v dd = 3v and 5v sinking dac = full scale dac = zero scale noise-voltage density vs. frequency (dac at midscale) max5723 toc30 frequency (hz) noise-voltage density (nv/ hz) 10k 1k 50 100 150 200 250 300 350 0 100 100k v dd = 5v, v ref = 2.5v internal v dd = 5v, v ref = 2.048v internal v dd = 5v, v ref = 3.5v (external) v dd = 5v, v ref = 4.096v internal max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
14 typical operating characteristics (continued) (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) 0.1hz to 10hz output noise, external reference (v dd = 5v, v ref = 4.5v) max5723 toc31 2v/div midscale unloaded v p-p = 12v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.048v) max5723 toc32 2v/div midscale unloaded v p-p = 13v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 2.5v) max5723 toc33 2v/div midscale unloaded v p-p = 15v 4s /div 0.1hz to 10hz output noise, internal reference (v dd = 5v, v ref = 4.096v) max5723 toc34 2v/div midscale unloaded v p-p = 16v 4s /div max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
15 typical operating characteristics (continued) (max5725, 12-bit performance, t a = +25c, unless otherwise noted.) watchdog timer period histogram max5723 toc38 frequency (hz) percent of population (%) 4 6 8 10 12 14 0 2 988 990 992 994 996 998 1000 1002 1004 1006 1008 1010 1012 1014 watchdog timer frequency vs. supply voltage max5723 toc39 supply voltage (v) watchdog timer frequency (hz) 5.1 4.7 4.3 3.9 3.5 3.1 980 985 990 995 1000 1005 975 2.7 5.5 watchdog timer frequency vs. temperature max5723 toc40 temperature (c) watchdog timer frequency (hz) 110 95 65 80 -10 5 20 35 50 -25 920 930 940 950 960 970 980 990 1000 1010 910 -40 125 v dd = 3v supply current vs. supply voltage max5723 toc37 input logic voltage (v) supply current (a) 4 3 2 1 500 1000 1500 2000 2500 3000 3500 0 05 sclk, csb, din, clr, and ldac swept from 0v to v ddio and v ddio to 0v v dd = 3v v ddio = 5v v ddio = 3v v ddio = 1.8v v ref drift vs. temperature max5723 toc35 temperature drift (ppm /c) percent of population (%) 4.3 4.1 4.0 3.9 3.7 3.6 3.4 3.3 3.2 3.0 2.9 5 10 15 20 25 0 2.8 4.4 reference load regulation max5723 toc36 reference output current (a) dv ref (mv) 450 400 350 300 250 200 150 100 50 -0.8 -0.6 -0.4 -0.2 0 -1.0 0 500 v ref = 2.048v, 2.5v, and 4.096v v dd = 5v internal reference max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
16 pin description pin configurations pin name function tssop wlp 1 d3 ref reference voltage input/output 2 d2 dac0 dac channel 0 voltage output 3 d1 out1 dac channel 1 voltage output 4 c1 out2 dac channel 2 voltage output 5 c2 out3 dac channel 3 voltage output 6 b2 out4 dac channel 4 voltage output 7 b1 out5 dac channel 5 voltage output 8 a1 out6 dac channel 6 voltage output 9 a2 out7 dac channel 7 voltage output 10 b3 v dd analog supply voltage 11 a3 v ddio digital supply voltage 12 a4 dout spi serial data output 13 a5 din spi serial data input 14 b5 sclk spi serial clock input 15 b4 csb spi chip-select input 16 c5 irq active-low open drain interrupt output. irq low indicates watchdog timeout. 17 c4 clr active-low asynchronous dac clear input 18 d5 ldac active-low asynchronous dac load input 19 d4 gnd ground 20 c3 m/ z dac output reset selection. connect m/ z to gnd for zero-scale and connect m/ z to v dd for midscale. 20 19 18 17 16 15 14 1 2 3 4 5 6 7 m/z gnd ldac clr out2 out1 out0 ref top view max5723 max5724 max5725 irq csb sclk out5 out4 out3 13 12 11 8 9 10 din dout v ddio v dd out7 out6 tssop + top view clr out2 csb out5 dout out6 max5723/max5724/max5725 + 1 2 34 a out3 m/z out4 v dd out7 v ddio b c wlp d irq sclk din 5 gnd out1 out0 ref ldac max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
17 detailed description the max5723/max5724/max5725 are 8-channel, low- power, 8-/10-/12-bit buffered voltage-output dacs. the 2.7v to 5.5v wide supply voltage range and low-power consumption accommodates most low-power and low- voltage applications. the devices present a 100k i load to the external reference. the internal output buffers allow rail-to-rail operation. an internal voltage reference is available with software-selectable options of 2.048v, 2.500v, or 4.096v. the devices feature a fast 4-wire spi/qspi/microwire/dsp-compatible serial interface to save board space and reduce the complexity in iso - lated applications interface. the max5723/max5724/ max5725 include a serial-in/parallel-out shift register, internal code and dac registers, a power-on-reset (por) circuit to initialize the dac outputs to zero scale (m/ z = 0) or midscale (m/ z = 1), and control logic. clr is available to asynchronously clear the dac out - puts to a user-programmable default value, independent of the serial interface. ldac is available to simultane - ously update selected dacs on one or more devices. the max5723/max5724/max5725 also feature user- configurable interface watchdog, with status indicated by the irq output. dac outputs (out_) the max5723/max5724/max5725 include internal buf - fers on all dac outputs, which provide improved load regulation for the dac outputs. the output buffers slew at 1v/ f s (typ) and drive resistive loads are as low as 2k i in parallel with as much as 500pf of capacitance. the analog supply voltage (v dd ) determines the maximum output voltage range of the devices since it powers the output buffers. under no-load conditions, the output buf - fers drive from gnd to v dd , subject to offset and gain errors. with a 2k load to gnd, the output buffers drive from gnd to within 200mv of v dd . with a 2k load to v dd , the output buffers drive from v dd to within 200mv of gnd. the dac ideal output voltage is defined by: out ref n d vv 2 = where d = code loaded into the dac register, v ref = reference voltage, n = resolution. internal register structure the user interface is separated from the dac logic to minimize digital feedthrough. within the serial interface is an input shift register, the contents of which can be routed to control registers, individual, or multiple dacs as determined by the user command. within each dac channel there is a code register followed by a dac latch register (see the detailed functional diagram ). the contents of the code register hold pending dac output settings which can later be loaded into the dac registers. the code register can be updated using both code and code_load user com - mands. the contents of the dac register hold the current dac output settings. the dac register can be updated directly from the serial interface using the code_load commands or can upload the current contents of the code register using load commands or the ldac logic input. the contents of both code and dac registers are main - tained during power-down states, so that when the dacs are powered on, they return to their previously stored output settings. any code or load commands issued during power-down states continue to update the register contents. once the device is powered up, each dac channel can be independently programmed with a desired return value using the return command. this becomes the value the code and dac registers will use in the event of any watchdog, clear or gate activity, as selected by the default command. hardware clr operations and sw_clear commands return the contents of all code and dac registers to their user-selected defaults. sw_reset commands will reset code and dac register contents to their m/ z selected initial codes. a sw_gate state can be used to momen - tarily hold selected dac outputs in their default posi - tions. the contents of code and dac registers can be manipulated by watchdog timer activity, enabling a variety of safety features. internal reference the max5723/max5724/max5725 include an internal precision voltage reference that is software selectable to be 2.048v, 2.500v, or 4.096v. when an internal reference is selected, that voltage is available on the ref output for other external circuitry (see the typical operating circuits ) and can drive loads down to 25k i . max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
18 external reference the external reference input has a typical input impedance of 100k i and accepts an input voltage from +1.24v to v dd . apply an external voltage between ref and gnd to use an external reference. the max5723/max5724/max5725 power up and reset to external reference mode. visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. m/ z input the max5723/max5724/max5725 feature a pin-select - able dac reset state using the m/ z input. upon a power- on reset, all code and dac data registers are reset to zero scale (m/ z = gnd) or midscale (m/ z = v dd ). m/ z is referenced to v dd (not v ddio ). in addition, m/ z must be valid at the time the device is powered upconnect m/ z directly to v dd or gnd. load dac ( ldac ) input the max5723/max5724/max5725 feature an active-low asynchronous ldac logic input that allows dac outputs to update simultaneously. connect ldac to v ddio or keep ldac high during normal operation when the device is controlled only through the serial interface. drive ldac low to update the dac outputs with data from the code registers. holding ldac low causes the dac registers to become transparent and code data is passed through to the dac registers immediately updat - ing the dac outputs. a software config command can be used to configure the ldac operation of each dac independently. clear ( clr ) input the max5723/max5724/max5725 feature an asynchro - nous active-low clr logic input that simultaneously sets all selected dac outputs to their programmable default states. driving clr low clears the contents of both the code and dac registers and also ignores any on-going spi command which modifies registers associ - ated with a dac configured to accept clear operations. to allow a new spi command, drive clr high, satisfying the t csc timing requirement. a software config com - mand can be used to configure the clear operation of each dac independently. watchdog feature the max5723/max5724/max5725 feature an interface watchdog timer with programmable timeout duration. this monitors the i/o interface for activity and integrity. if the watchdog is enabled, the host processor must write a valid command to the device within the timeout period to prevent a timeout. if the watchdog is allowed to timeout, selected dac outputs are returned to the programmable default state, protecting the system against control faults. by default, all watchdog features are disabled; users wishing to activate any watchdog feature must configure the device accordingly. individual dac channels can be configured using the config command to accept the watchdog alarm and to gate, clear, or hold their out - puts in response to an alarm. a watchdog refresh event and watchdog behavior upon timeout is defined by a programmable safety level using the wdog_config command. irq output the max5723/max5724/max5725 feature an active-low open-drain interrupt output indicating to the host when a watchdog timeout has occurred. interface power supply (v ddio ) the max5723/max5724/max5725 feature a separate supply input (v ddio ) for the digital interface (1.8v to 5.5v). connect v ddio to the i/o supply of the host pro - cessor. spi serial interface the max5723/max5724/max5725 4-wire serial inter - face is compatible with microwire, spi, qspi, and dsps. the interface provides three inputs, sclk, csb, and din. the chip-select input (csb, active-low) frames the data loaded through the serial data input (din). following a csb input high-to-low transition, the data is shifted in synchronously and latched into the input register on each falling edge of the serial clock input (sclk). each serial operation word is 24-bits long. the dac data is left justified as shown in table 1 . the serial table 1. format dac data bit positions part b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 max5723 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x max5724 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x max5725 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
19 input register transfers its contents to the destination registers after loading 24 bits of data on the 24th sclk falling edge. to initiate a new spi operation, drive csb high and then low to begin the next operation sequence, being sure to meet all relevant timing requirements. during csb high periods, sclk is ignored, allowing communication to other devices on the same bus. spi operations consisting of more than 24 sclk cycles are executed on the 24th sclk falling edge, using the first three bytes of data available. spi operations consisting of less than 24 sclk cycles will not be executed. the content of the spi operation consists of a command byte followed by a two-byte data word. the dout phase for all spi_read commands is deter - mined by the readback command used, allowing the selection of the sclk dout update edge best suited to the digital i/o implementation, maximizing data transfer speed and/or timing margin. guaranteed non-zero dout hold times allow the micro - processor to strobe dout on the same edge as the max5723/max5724/max5725 updates for fastest spi read mode transfers. for example, if dpha = 0 is used, the max5723/max5724/max5725 update dout in response to sclk falling edges 8-23, while a micropro - cessor (p) with low data hold time requirements can strobe in the dout data on sclk falling edges 9-24. the device supports readback speeds of up to 25mhz for a microprocessor with 5ns data input setup require - ments and allowing 35ns for t dot at v ddio > 2.7v. variable dout phase also supports microprocessors with longer data input hold time requirements. for example, if dpha = 1 is used, the max5723/max5724/ max5725 updates dout in response to sclk rising edges 9-24 while the microprocessor can strobe in the dout data on sclk falling edges 9-24. the device supports readback speeds up to 12.5mhz for a p with 5ns data input setup requirements and allowing 35ns for t dot (assuming 50% duty cycle sclk). for improved readback speed while monitoring device status, the spi_read_status command repeats the device status information for multiple bits, allowing polling of the device at maximum interface speeds (up to 50mhz when the readback strobe is placed away from dout transition edges). this transfer speed can - not be achieved for other forms of readback using the spi_read_data command, where more dout bus transitions occur. figure 1 shows the timing diagram for the complete 4-wire serial interface transmission. the dac code settings (d) for the max5723/max5724/max5725 are accepted in an offset binary format (see table 1 ). otherwise, the expected data format for each command is listed in table 2 . see figure 2 for an example of a typical spi circuit application. spi user-command register map this section lists the user-accessible commands and registers for the max5723/max5724/max5725. table 2 provides detailed information about the command registers. figure 2. typical spi application circuit max5723 max5724 max5725 csb sclk din dout csb sclk din dout csb csb3 csb2 sclk din csb1 r pu = 5ki +5v sclk mosi miso irq c irq irq max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
20 table 2. spi commands summary command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description configuration and software commands wdog 0 0 0 1 x x x x timeout selection[11:4] timeout selection[3:0] wd_mask safety level 00: low 01: med 10: high 11: max x updates watchdog settings and safety levels ref 0 0 1 0 0 ref power 0 = dac 1 = on ref mode 00 = ext 01 = 2.5v 10 = 2.0v 11 = 4.1v x x x x x x x x x x x x x x x x sets the reference operating mode. ref power (b18): 0 = internal reference is only powered if at least one dac is powered 1 = internal reference is always powered sw_gate_ clr 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 removes any existing gate condition sw_gate_ set 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 initiates a gate condition wd_refresh 0 0 1 1 0 0 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 refreshes the watchdog timer wd_reset 0 0 1 1 0 0 1 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 reset the watchdog time out alarm status and refreshes the watchdog timer sw_clear 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 executes a software clear (all code and dac registers cleared to their default values) sw_reset 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 executes a software reset (all code, dac, and control registers returned to their power-on reset values) config 0 1 0 1 0 0 0 0 dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 wdog config. 00: dis 01: gate 10: clr 11: hold gate_enb ldac_enb clear_enb x x x configures selected dac watchdog, gate, load, and clear operations. dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
21 table 2. spi commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description power 0 1 0 0 0 0 0 0 dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 power mode 00 = normal 01 = pd1k i 10 = pd 100k i 11 = pd hi-z x x x x x x sets the power mode of the selected dacs (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) default 0 1 1 0 0 0 0 0 dac7 dac6 dac5 dac4 dac3 dac2 dac1 dac0 default values : 000: m z 001: zero 010: mid 011: full 100: return 101+: no effect sets the default code settings for selected dacs. note, dacs in return mode programmable return codes. (dacs selected with a 1 in the corresponding dacn bit are updated, dacs with a 0 in the corresponding dacn bit are not impacted) dac commands returnn 0 1 1 1 dac selection return register data[11:4] return register data[3:0] x x x x writes data to the selected return register(s) coden 1 0 0 0 dac selection code register data[11:4] code register data[3:0] x x x x writes data to the selected code register(s) loadn 1 0 0 1 dac selection x x x x x x x x x x x x x x x x transfers data from the selected code registers to the selected dac register(s) coden_ load_all 1 0 1 0 dac selection code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating all dac registers coden_ loadn 1 0 1 1 dac selection code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the selected code register(s) while updating selected dac register(s) code_all 1 1 0 0 0 0 0 0 code register data[11:4] code register data[3:0] x x x x writes data to all code registers max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
22 table 2. spi commands summary (continued) command b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 description load_all 1 1 0 0 0 0 0 1 x x x x x x x x x x x x x x x x updates all dac latches with current code register data code_all load_all 1 1 0 0 0 0 1 0 code register data[11:4] code register data[3:0] x x x x simultaneously writes data to the all code registers while updating all dac registers return_all 1 1 0 0 0 0 1 1 return register data[11:4] return register data[3:0] x x x x writes data to all return registers spi_data_ request 1 1 0 1 dac selection inc data sel [1:0] 00 = dac 01 = code 10 = ret 11 = wdt x x x x x x x x x x x x setup data request for readback. inc indicates if the dac selection is incremented to the next dac after each spi_read _data operation data sel[1:0] indicates the data content to be read back spi_read status 1 1 1 0 0 0 x x x x x x x x x x x x x x x x x x dpha = 0 readback status 1 1 1 0 0 1 x x x x x x x x x x x x x x x x x x dpha = 1 readback status spi_read data 1 1 1 0 1 0 x x x x x x x x x x x x x x x x x x dpha = 0 readback requested data 1 1 1 0 1 1 x x x x x x x x x x x x x x x x x x dpha = 1 readback requested data no operation commands no operation 1 1 0 0 0 1 x x x x x x x x x x x x x x x x x x these commands will have no effect on the device, but will refresh the watchdog timer if safety level is set to low. 1 1 0 0 1 0 x x x x x x x x x x x x x x x x x x 1 1 0 0 1 1 x x x x x x x x x x x x x x x x x x reserved commands: any commands not specifically listed above are reserved for maxim internal use only. max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
23 returnn command the return command (b[23:20] = 0111) sets the pro - grammable default return value. this value is used for all future watchdog, clear, and gate operations when ret is selected for the dac using the default com - mand. issuing this command with dac_address set to all dacs will program the value for all return registers and is equivalent to return_all. note: this command is inaccessible when a watchdog timeout has occurred if the watchdog timer is configured for safety level = high or max. coden command the coden command (b[23:20] = 1000) updates the code register contents for the selected dac(s). changes to the code register content based on this command will not affect dac outputs directly unless the ldac input is in a low state or the dac latch has been configured as transparent using the config command. issuing this command with dac_address set to all dacs will program the value for all code registers and is equivalent to code_all. loadn command the loadn command (b[23:20] = 1001) updates the dac register content for the selected dac(s) by upload - ing the current contents of the selected code register(s) into the selected dac register(s). channels for which code content has not been modified since the last load or ldac operation will not be updated to reduce digital crosstalk. issuing this command with dac_address set to all dacs will update the contents of all dac registers and is equivalent to load_all. coden_loadn command the coden_loadn command (b[23:20] = 1011) updates the code register contents for the selected dac(s) as well as the dac register content of the select - ed dac(s). channels for which code content has not been modified since the last load or ldac operation will not be updated to reduce digital crosstalk. issuing this command with dac_address set to all dacs is equivalent to the code_all_load_all (b[23:16] = 1100_0010) command. coden_load_all command the coden_load_all command (b[23:20] = 1010) updates the code register contents for the selected dac(s) as well as the dac register content of all dacs. channels for which code content has not been modified since the last load or ldac operation will not be updat - ed to reduce digital crosstalk. issuing this command with dac_address set to all dacs will update the code and dac register contents of all dacs and is equivalent to code_all_load_all. note this command by defini - tion will modify at least one code register; to avoid this use the load command with dac_address set to all dacs or the load_all command. code_all command the code_all command (b[23:16] = 1100_0000) updates the code register contents for all dacs. load_all command the load_all command (b[23:16] = 1100_0001) updates the dac register content for all dacs by upload - ing the current contents of the code registers to the dac registers. code_all_load_all command the code_all_load_all command (b[23:16] = 1100_0010) updates the code register contents for all dacs as well as the dac register content of all dacs. return_all command the return_all command (b[23:16] = 1100_0011) updates the return register contents for all dacs. no_op commands command all unused commands in the space (b[23:16] = 1100_01xx or 1100_1xxx) have no effect on the device, but will refresh the watchdog timer (if active) with the safety level set to low. table 3. dac selection b19 b18 b17 b16 dac selected 0 0 0 0 dac0 0 0 0 1 dac1 0 0 1 0 dac2 0 0 1 1 dac3 0 1 0 0 dac4 0 1 0 1 dac5 0 1 1 0 dac6 0 1 1 1 dac7 1 x x x all dacs max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
24 wdog command the wdog command (b[23:20] = 0001) updates the watchdog timeout settings and safety levels for the device. timeout thresholds are selected in 1ms incre - ments (1ms to 4095ms are available). the wd_mask bit can be used to mask the irq operation in response to the watchdog status, if wd_mask = 1, watchdog alarms will not assert irq . the watchdog alarm status (wd bit) can be polled using the available spi status readback com - mands regardless of wd_mask settings. a write to this register will not reset a previously triggered watchdog alarm (use the wd_reset command for this purpose). the watchdog timer refresh and timeout behavior is defined by the programmable safety level below. available safety levels (wl[1:0]): low (00): watchdog timer will refresh with the execution of any valid user mode command or no-op. any success - ful slave address acknowledge qualifies to restart the watchdog timer (run to the ninth scl edge), regardless of the command which follows. issuing hardware clr or ldac falling edge will also refresh the watchdog timer. a triggered watchdog alarm does not prevent writes to any register. ldac and clr inputs still function after a watchdog timeout event. medium (01): a wd_refresh command must be execut - ed in order to refresh the watchdog timer. other commands as well as ldac or clr activity do not refresh the watch - dog timer. a triggered watchdog alarm does not prevent writes to any register. ldac and clr inputs still function after a watchdog timeout event. high (10): a wd_refresh command must be executed to refresh the watchdog timer. other commands as well as ldac or clr activity do not refresh the watchdog timer. a triggered watchdog alarm prevents execution of all power, ref, config, default, and return commands. ldac and clr inputs still function after a watchdog timeout event. max (11): a wd_refresh command must be executed to refresh the watchdog timer. other commands, as well as ldac or clr activity, do not refresh the watchdog timer. a triggered watchdog alarm prevents execution of all power, ref, config, default, and return com - mands. ldac and clr are gated and do not function after a watchdog timeout event. table 5. watchdog safety level protection * unless otherwise affected by watchdog hold or clr configurations as set by the config command. see the config register definition for details. table 4. wdog command format watchdog safety level any command refreshes wdt clr / ldac refreshes wdt sw_reset plus wd_rfrs refreshes wdt all registers accessible after wdt timeout* clr / ldac affect dac registers after wdt timeout* 00 (low) x x x x x 01 (med) x x x 10 (high) x x 11 (max) x b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 1 x x x x c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 wdm wl1 wl0 x wdog command dont care timeout selection timeout selection wd_mask wdog safety level: 00: low 01: med 10: high 11: max dont care default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
25 table 6. ref command format ref command the ref command (b[23:20] = 0010) updates the global reference setting used for all dac channels. if an internal reference mode is selected, bit rf2 (b18) defines the reference power mode. if rf2 is set to zero (default), the reference will be powered down any time all dac chan - nels are powered down (i.e. the device is in standby mode). if rf2 is set to one, the reference will remain pow - ered even if all dac channels are powered down, allow - ing continued operation of external circuitry (note in this mode the low current shutdown state is not available). this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. sw_gate_clr command the sw_gate_clr command (b[23:0] = 0011_0000_ 1001_0110_0011_0000) will remove any existing gate condition initiated by a previous sw_gate_set comand. sw_gate_set command the sw_gate_set command (b[23:0] = 0011_0001_ 1001_0110_0011_0000) will initiate a gate condition. any dacs configured with gtb = 0 (see the config command section) will have their outputs held at the selected default value until the gate condition is later removed by a subsequent sw_gate_clr command. while in gate mode, the code and dac registers con - tinue to function normally and are not reset (unless reset by a watchdog timeout). wd_refresh command the wd_refresh command (b[23:0] = 0011_0010_ 1001_0110_0011_0000) will refresh the watchdog timer. this is the only command which will refresh the watch - dog timer if the device is configured with a safety level of medium, high, or max. use this command to prevent the watchdog timer from timing out. wd_reset command a wd_reset command (b[23:0] = 0011_0011_ 1001_0110_0011_0000) will reset the watchdog interrupt (timeout) status and refresh the watchdog timer. use this command to reset the irq timeout condition after the watchdog timer has timed out. any dacs impacted by an existing timeout condition will return to normal operation. sw_clear command a software clear command (b[23:0] = 0011_0100_ 001_0110_0011_0000) will clear the contents of the code and dac registers to the default state for all channels configured with clb = 0 (see config command). sw_reset command a software reset command (b[23:0] = 0011_0101_ 1001_0110_0011_0000) will reset all code, dac, and configuration registers to their defaults (including power, default, config, wdog, and ref regis - ters), simulating a power-on reset. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 rf2 rf1 rf0 x x x x x x x x x x x x x x x x ref command reserved 0 = dac controlled 1 = always on ref mode: 00: ext 01: 2.5v 10: 2.0v 11: 4.0v dont care dont care default value 0 0 0 x x x x x x x x x x x x x x x x command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
26 power command the power command (b[23:20] = 0100) updates the power mode settings of the selected dacs. dacs that are not selected do not update their power settings in response to the command. the new power setting is determined by bits pd[1:0] (b[7:6]) while the affected dac(s) are selected using b[15:8]). if all dacs are pow - ered down and the rf2 bit is not set, the device enters a standby mode (all analog circuitry is disabled). this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. available power modes (pd[1:0]): normal (00): dac channel is active (default). pd 1k (01): power down with 1k termination to gnd. pd 100k (10): power down with 100k termination to gnd. pd hi-z (11): power down with high-impedance output. config command the config command (b[23:16] = 0101) updates the watchdog, gate, load, and clear mode settings of the selected dacs. dacs which are not selected do not update their settings in response to the command. the new mode settings to be written are determined by bits b[7:3] while the affected dac(s) are selected by b[15:8]. this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. watchdog configuration: wdog config settings are written by wc[1:0] (b[7:6]): disable (wc = 00): watchdog timeout does not affect the operation of the selected dac. gate (wc = 01): dac code is gated to default value in response to watchdog timeouts. unless otherwise prohibited by the watchdog safety level, ldac , clr , and write operations to the code and dac registers are accepted but will not be reflected on the dac output until the watchdog timeout status is reset. clr (wc = 10): code and dac register contents are cleared to default value in response to watchdog time - outs. all writes to code and dac registers are ignored and ldac or clr input activity has no effect until the watchdog timeout status is reset, regardless of watchdog safety level. hold (wc = 11): dac code is held at its previously programmed value in response to watchdog timeout. all writes to dac and code registers are ignored and ldac or clr input activity has no effect until the watch - dog timeout status is reset, regardless of watchdog safety level. note: for the watchdog to timeout and have an impact, the function must first be enabled and configured using the wdog command. table 7. power command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 0 0 0 0 7 6 5 4 3 2 1 0 pd1 pd0 x x x x x x power command reserved multiple dac selection power mode: 00 = normal 01 = 1k w 10 = 100k w 11 = hi-z dont care default value : 1 1 1 1 1 1 1 1 0 0 x x x x x x command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
27 table 8. config command format gate configuration: the dac gate setting is written by gtb (b5); gate operation is as follows: gtb = 0: enables software gating function (default), dac outputs are gated to their default settings as long as the device remains in gate mode (set by sw_gate_ set and removed by sw_gate_clr). gtb = 1: disable software gating function, dac outputs are not impacted by gate mode. load configuration: the ldac_enb setting is written by ldb (b4); ldac_enb operation is as follows: ldb = 0: dac latch is operational, enabling ldac and load functions (default). ldb = 1: dac latch is transparent, the code register content controls the dac output directly. clear configuration: clear_enb setting is written by clb (b3); clear_enb operation is as follows: clb = 0: clear input and command functions impact the dac (default), clearing code and dac registers to their default value. clb = 1: clear input and command functions have no effect on the dac. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 1 0 0 0 0 7 6 5 4 3 2 1 0 wc1 wc0 gtb ldb clb x x x config command reserved multiple dac selection wdog config: 00: disable 01: gate 10: clr 11: hold gate_enb ldac_enb clear_enb dont care default value 1 1 1 1 1 1 1 1 0 0 0 0 0 x x x command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
28 default command the default command (b[23:20] = 0110) selects the default value for selected dacs. dacs which are not selected do not update their default settings in response to the command. these default values are used for all future watchdog, clear, and gate operations. the new default setting is determined by bits df[2:0] (b[7:5]) while the affected dac(s) are selected using b[15:8]. this command is inaccessible when a watchdog timeout has occurred and the watchdog timer is configured with a safety level of high or max. note the selected default values do not apply to resets initiated by sw_reset commands or supply cycling, both of which return all dacs to the values determined by the m/ z input and reset this register to m/ z mode. available default values (df[2:0]): m/ z (000): dac channel defaults to value as selected by the m/ z input (default). zero (001): dac channel defaults to zero scale. mid (010): dac channel defaults to midscale. full (011): dac channel defaults to full scale. return (100): dac channel defaults to the value pro - grammed by the return command. no effect (101, 110, 111): dac channel default behavior is unchanged. table 9. default command format b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 1 1 0 0 0 0 0 7 6 5 4 3 2 1 0 df2 df1 df0 x x x x x default command reserved multiple dac selection default values: 000: m/ z 001: zero 010: mid 011: full 100: return 101+: no effect dont care default value 1 1 1 1 1 1 1 1 0 0 0 x x x x x command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
29 spi_data_request command the spi_data_request command (b[23:20] = 1101) sets up the data request for future spi_read_data operations. spi_read_data is used to fetch the current settings of the internal code, dac, or return registers for each channel or the watchdog configuration (wdog) settings or the device. the dac address provided tells the part which channel location data is to be read back by the next spi_read_data command (see table 3 ). setting the dac address greater than the number of available dacs will read back channel 0 content. the inc bit tells the device how the next readback will update the dac address pointer: 0 = fix the address pointer (all further readbacks con - tinue at the current address). 1 = increment the address pointer (further readbacks continue at the next address, with rollover, default). the sel[1:0] bits tells the part what type of data is requested: dac (00): dac register data (current dac latch data, not subject to gating status, default). code (01): code register data. ret (10): return register data. wdt (11): wdog register data (dac selection does not apply). table 10. spi_data_request command format table 11. spi_read_status command format spi_read_status command the spi_read_status command (b[23:18] = 111000 for dpha = 0, b[23:18] = 111001 for dpha = 1) reads back the watchdog timer and clr pin status (inten - tionally repeated to allow maximum interface speeds) through dout. din[18] selects the dout phase (dpha) to be used (see the spi serial interface timing diagram in figure 1 for details). wd_stat indicates a watchdog timeout condition. it reads 0 during normal operation, 1 during a timeout. wd_stat is not masked by the wd_mask bit in the wdog_config command. clr _stat indicates the line level of the clr pin. 0 indi - cates the clr input is or was asserted (grounded) during the current spi operation. 1 indicates the clr input is not currently asserted (v ddio level). b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 0 1 dac selection inc sel[1:0] x x x x x x x x x x x x x spi_data_request dac selection increment data selection 00: dac 01: code 10: ret 11: wdt dont care dont care default value 0 0 0 0 1 0 0 x x x x x x x x x x x x x command byte data high byte data low byte b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 0 0 0 x x x x x x x x x x x x x x x x x x spi_read_status (dpha = 0) dout = wd_stat (repeated) dout = clr _stat (repeated) 1 1 1 0 0 1 x x x x x x x x x x x x x x x x x x spi_read_status (dpha = 1) dout = wd_stat (repeated) dout = clr _stat (repeated) command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
30 table 12. spi_read_data command format spi_read_data command the spi_read_data command (b[23:18] = 111010 for dpha = 0, b[23:18] = 111011 for dpha = 1) reads back the data requested using the spi_data_request com - mand through dout. din[18] selects the dout phase (dpha) to be used (see figure 1 for details, and the spi timing characteristics in the electrical characteristics for a complete listing of readback speed capabilities based on the dpha selec - tion). the spi_read_data command provides register and address data as defined by the spi_data_request configuration sel bits. spi_read_data also increments the channel address pointer if configured to do so by the spi_data_request inc bit, the address readback is the address corresponding to the data returned. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 0 1 0 x x x x x x x x x x x x x x x x x x spi_read_data (dpha = 0, sel = 00) dout = dac[11:4] dout = dac[3:0] address[3:0] spi_read_data (dpha = 0, sel = 01) dout = code[11:4] dout = code[3:0] address[3:0] spi_read_data (dpha = 0, sel = 10) dout = return[11:4] dout = ret[3:0] address[3:0] spi_read_data (dpha = 0, sel = 11) dout = wdog[15:8] dout = wdog[7:1] 0 1 1 1 0 1 1 x x x x x x x x x x x x x x x x x x spi_read_data (dpha = 1, sel = 00) dout = dac[11:4] dout = dac[3:0] address[3:0] spi_read_data (dpha = 1, sel = 01) dout = code[11:4] dout = code[3:0] address[3:0] spi_read_data (dpha = 1, sel = 10) dout = return[11:4] dout = ret[3:0] address[3:0] spi_read_data (dpha = 1, sel = 11) dout = wdog[15:8] dout = wdog[7:1] 0 command byte data high byte data low byte max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
31 applications information power-on reset (por) when power is applied to v dd and v ddio , the dac out - put is set to zero scale. to optimize dac linearity, wait until the supplies have settled and the internal setup and calibration sequence completes (200 f s, typ). power supplies and bypassing considerations bypass v dd and v ddio with high-quality ceramic capac - itors to a low-impedance ground as close as possible to the device. minimize lead lengths to reduce lead induc - tance. connect the gnd to the analog ground plane. layout considerations digital and ac transient signals on gnd can create noise at the output. connect gnd to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance. use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star connect all ground return paths back to the max5723/max5724/max5725 gnd. carefully layout the traces between channels to reduce ac cross-coupling. do not use wire-wrapped boards and sockets. use shielding to minimize noise immu - nity. do not run analog and digital signals parallel to one another, especially clock signals. avoid routing digital lines underneath the max5723/max5724/max5725 package. definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl p 1 lsb, the dac guarantees no missing codes and is monotonic. if the magnitude of the dnl r 1 lsb, the dac output may still be monotonic. offset error offset error indicates how well the actual transfer function matches the ideal transfer function. the offset error is calculated from two measurements near zero code and near maximum code. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. zero-scale error zero-scale error is the difference between the dac output voltage when set to code zero and ground. this includes offset and other die level nonidealities. full-scale error full-scale error is the difference between the dac output voltage when set to full scale and the reference volt - age. this includes offset, gain error, and other die level nonidealities. settling time the settling time is the amount of time required from the start of a transition, until the dac output settles to the new output value within the converters specified accuracy. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse a major carry transition occurs at the midscale point where the msb changes from low to high and all other bits change from high to low, or where the msb changes from high to low and all other bits change from low to high. the duration of the magnitude of the switching glitch during a major carry transition is referred to as the digital-to-analog glitch impulse. although all bits change, larger steps may lead to larger glitch energy. the digital-to-analog power-up glitch is the duration of the magnitude of the switching glitch that occurs as the device exits power-down mode. max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
32 detailed functional diagram out0 out1 buffer 0 channel 0 dac control logic dac channel 0 dac channel 1 power-down 1ki 100ki code load clear / reset gate/ clear / reset code register 0 dac latch 0 8- /1 0- /1 2- bit dac0 din sclk csb v ddio dout clr ldac spi serial interface control logic ref r in 100ki internal/external reference (user option) max5723 max5724 max5725 v dd gnd irq out7 buffer 7 channel 7 dac control logic dac channel 7 power-down 1ki 100ki code load clear / reset gate/ clear / reset code register 7 dac latch 7 8- /1 0- /1 2- bit dac7 out2 dac channel 2 out3 dac channel 3 out4 dac channel 4 out5 dac channel 5 out6 dac channel 6 watchdog timer m/z por max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
33 typical operating circuits c csb sclk din clr irq m/z dout note: unipolar operating circuit, one channel show n dac out gnd ldac v ddio v dd ref 100nf 100nf 4.7f r pu = 5ki max5723 max5724 max5725 dac c csb sclk din clr irq m/z dout out gnd ldac v ddio v dd ref 100nf 100nf 4.7f r pu = 5ki r1 r2 r1 = r2 max5723 max5724 max5725 note: bipolar operating circuit, one channel show n max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
34 ordering information note: all devices are specified over the -40c to +125c temperature range. +denotes a lead(pb)Cfree/rohs-compliant package. t = tape and reel. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. part temp range pin-package resolution (bit) max5723 aup+ -40c to +125c 20 tssop 8 max5724 aup+ -40c to +125c 20 tssop 10 max5725 aaup+ -40c to +125c 20 tssop 12 max5725awp+t -40c to +125c 20 wlp 12 max5725baup+ -40c to +125c 20 tssop 12 package type package code outline no. land pattern no. 20 tssop u20+1 21-0066 90-0116 20 wlp w202c2+1 21-0059 refer to application note 1891 max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 35 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc . revision history revision number revision date description pages changed 0 3/12 initial release 1 11/12 revised the ordering information , electrical characteristics , typical operating characteristics , pin configuration, pin description, figure 1, and the dac outputs (out_) , coden_loadn command , and offset error sections. 3, 5, 8, 10C13, 15C18, 23, 31, 34 2 2/13 released the max5723/max5724/max5725b. updated the electrical characteristics global and note 3. 2C8, 34 max5723/max5724/max5725 ultra-small, octal-channel, 8-/10-/12-bit buffered output dacs with internal reference and spi interface

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